Field of the Invention
The invention relates to a method for configuring and operating an installation of memory modules that do not have signal-conditioning devices and that are configured on slots of a system. Initially a system motherboard that has the slots and a number of memory modules without signal-conditioning devices are provided.
In modular electronic systems with variable configurations, a system motherboard with one or a plurality of slots is normally provided. Depending on the requirements of the system or the configuration level of the system, the slots are in each case equipped with a memory module or are unequipped. The interfaces of the memory modules are by necessity identical or compatible with one another.
A typical example of a modular memory system of this type is a computer system (PC, workstation, server) with expandable base memory, whereby slots for memory modules in the form of plug-in sockets are provided on the system motherboard and, depending on the required size of the base memory, are equipped with memory modules. Furthermore, the plug-in sockets in each case establish an electrical connection between signal lines on the substrate and contact areas on the memory modules. The memory modules are normally provided in the form of SIMMs (single inline memory modules) or DIMMs (dual inline memory modules).
The plug-in sockets enable simple exchange or simple retrofitting of the memory modules.
The requirements for the design of the bus system signal lines increase with higher clock rates and data transmission rates to and from the memory modules.
A data transmission rate of 667 Mbit per second and per data signal (Mbit/s/pin) is proposed here for DDRII bus systems for DDR-DRAMs (double data rate dynamic random access memories), and a data transmission rate of 1.2 Gbit/s/pin is proposed for DDRIII bus systems. With these data transmission rates, substantial outlay is required to ensure signal integrity at a respective receive location of data signals transmitted on the bus system signal lines, since a parasitic capacitance allocated to the signal line is too high to be able to be recharged quickly enough by a bus-monitoring chip or by memory chips arranged on the memory modules. Furthermore, signal integrity is adversely affected by reflections at interference points as the clock rate increases.
It is therefore proposed to insert buffer chips for signal conditioning between the memory chips and the bus system signal lines, similar to those already known from DDRI bus systems for control and address signals.
In DDRI bus systems, for configurations with two and more memory modules, the memory modules are provided with signal-conditioning devices such as buffer chips and/or buffer memories (registered DIMMs). Since the bus system signal lines are then no longer connected to all memory chips arranged on the memory modules, but to one memory chip only, the capacitive load of the signal lines represented by the memory module and the number of interference points are reduced. The disadvantage of this solution is the need for a delay cycle (latency) between the transmission of control and address signals on the control and address lines on the one hand and the transmission of data on data lines on the other hand. In a write cycle, the control and address signals are initially transmitted to a buffer or buffer memory and are only transmitted to the memory chips in a following cycle together with the data signals which are output following a one-cycle delay.
The delay cycle significantly reduces the data transmission rate, particularly in the case of random address accesses.
If signal-conditioning devices are implemented for DDRII and DDRIII bus systems, the signal-conditioning devices must be provided either on the memory modules or on the system motherboard.
Both solutions result in serious disadvantages.
A configuration of the signal-conditioning devices on the memory modules on the one hand increases the cost of the memory modules and, on the other hand, testing of the memory modules is rendered difficult. The reason for this is that, as the memory chips are no longer directly accessible via the memory module interface, the outlay required, for example, to test for adequate time conditions (time margins, skew) in the memory chips is considerably increased.
If, however, the signal-conditioning devices are provided on the system motherboard, the signal-conditioning devices are also functional for configurations in which they are not required, and reduce the functionality (performance) of the memory modules due to the then essentially superfluous delay cycles.